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  1. <!doctype html>
  2. <html>
  3. <head>
  4. <meta charset="utf-8">
  5. <title>CodeMirror: Verilog mode</title>
  6. <link rel="stylesheet" href="../../lib/codemirror.css">
  7. <script src="../../lib/codemirror.js"></script>
  8. <script src="verilog.js"></script>
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  10. <style>.CodeMirror {border: 2px inset #dee;}</style>
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  12. <body>
  13. <h1>CodeMirror: Verilog mode</h1>
  14. <form><textarea id="code" name="code">
  15. /* Verilog demo code */
  16. module butterfly
  17. #(
  18. parameter WIDTH = 32,
  19. parameter MWIDTH = 1
  20. )
  21. (
  22. input wire clk,
  23. input wire rst_n,
  24. // m_in contains data that passes through this block with no change.
  25. input wire [MWIDTH-1:0] m_in,
  26. // The twiddle factor.
  27. input wire signed [WIDTH-1:0] w,
  28. // XA
  29. input wire signed [WIDTH-1:0] xa,
  30. // XB
  31. input wire signed [WIDTH-1:0] xb,
  32. // Set to 1 when new data is present on inputs.
  33. input wire x_nd,
  34. // delayed version of m_in.
  35. output reg [MWIDTH-1:0] m_out,
  36. // YA = XA + W*XB
  37. // YB = XA - W*XB
  38. output wire signed [WIDTH-1:0] ya,
  39. output wire signed [WIDTH-1:0] yb,
  40. output reg y_nd,
  41. output reg error
  42. );
  43. // Set wire to the real and imag parts for convenience.
  44. wire signed [WIDTH/2-1:0] xa_re;
  45. wire signed [WIDTH/2-1:0] xa_im;
  46. assign xa_re = xa[WIDTH-1:WIDTH/2];
  47. assign xa_im = xa[WIDTH/2-1:0];
  48. wire signed [WIDTH/2-1: 0] ya_re;
  49. wire signed [WIDTH/2-1: 0] ya_im;
  50. assign ya = {ya_re, ya_im};
  51. wire signed [WIDTH/2-1: 0] yb_re;
  52. wire signed [WIDTH/2-1: 0] yb_im;
  53. assign yb = {yb_re, yb_im};
  54. // Delayed stuff.
  55. reg signed [WIDTH/2-1:0] xa_re_z;
  56. reg signed [WIDTH/2-1:0] xa_im_z;
  57. // Output of multiplier
  58. wire signed [WIDTH-1:0] xbw;
  59. wire signed [WIDTH/2-1:0] xbw_re;
  60. wire signed [WIDTH/2-1:0] xbw_im;
  61. assign xbw_re = xbw[WIDTH-1:WIDTH/2];
  62. assign xbw_im = xbw[WIDTH/2-1:0];
  63. // Do summing
  64. // I don't think we should get overflow here because of the
  65. // size of the twiddle factors.
  66. // If we do testing should catch it.
  67. assign ya_re = xa_re_z + xbw_re;
  68. assign ya_im = xa_im_z + xbw_im;
  69. assign yb_re = xa_re_z - xbw_re;
  70. assign yb_im = xa_im_z - xbw_im;
  71. // Create the multiply module.
  72. multiply_complex #(WIDTH) multiply_complex_0
  73. (.clk(clk),
  74. .rst_n(rst_n),
  75. .x(xb),
  76. .y(w),
  77. .z(xbw)
  78. );
  79. always @ (posedge clk)
  80. begin
  81. if (!rst_n)
  82. begin
  83. y_nd <= 1'b0;
  84. error <= 1'b0;
  85. end
  86. else
  87. begin
  88. // Set delay for x_nd_old and m.
  89. y_nd <= x_nd;
  90. m_out <= m_in;
  91. if (x_nd)
  92. begin
  93. xa_re_z <= xa_re/2;
  94. xa_im_z <= xa_im/2;
  95. end
  96. end
  97. end
  98. endmodule
  99. </textarea></form>
  100. <script>
  101. var editor = CodeMirror.fromTextArea(document.getElementById("code"), {
  102. lineNumbers: true,
  103. mode: "text/x-verilog"
  104. });
  105. </script>
  106. <p>Simple mode that tries to handle Verilog-like languages as well as it
  107. can. Takes one configuration parameters: <code>keywords</code>, an
  108. object whose property names are the keywords in the language.</p>
  109. <p><strong>MIME types defined:</strong> <code>text/x-verilog</code> (Verilog code).</p>
  110. </body>
  111. </html>